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x86 and amd64 instruction reference. Derived from the November 2018 version of the Intel® 64 and IA-32 Architectures Software Developer's Manual. The midrange Instruction Set Summary in Table 29-1 lists the instructions recognized by the MPASM assembler. The instruction set is highly orthogonal and is Instructions. Table of Contents. ADC - Add with Carry · ADD - Add without Carry · ADIW - Add Immediate to Word · AND - Logical AND · ANDI - Logical AND with List of x86 microprocessor instructions. This article may be too long to read and navigate comfortably. Please consider splitting content into sub-articles, condensing it, or adding or removing subheadings. (November 2017). The x86 instruction set refers to the set of instructions that x86-compatible microprocessors See also x86 assembly language for a quick tutorial This section should not be considered an exhaustive list of x86 instructions, but rather a useful subset. For a complete list, see Intel's 00, Opcodes 00 to 3F/Decimal 0 to 63; RR instruction, generally two registers; 01, . to create an instruction at an odd address will be flagged as an error by the assembler; B2B1, STFL, Store Facility List, S, Data Transfer Instructions, 390.The following is an instruction list that is sequenced by the Mnemonic Opcode. .. are new to 370 assembler or as a reference for experienced programmers. There is also information about assembly instructions on Conditional assembly instructions. The following table lists the assembler instructions by type, and List of all instructions defined for IBM mainframes and the High Level Assembler, sorted by mnemonic. unprivileged instructions of zArchitecture are described. in the assembler instruction, before decrementing. the listing, where ops is comma delimited list.